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mos integrated circuit m m m m pd16641 source driver for 240-output tft-lcd (64 gray scales) 1998 ? document no. s10565ej1v0ds00 (1st edition) date published may 1998 n cp(k) printed in japan data sheet description the m pd16641 is a source driver for tft-lcd 64 gray scale displays. its logic circuit operates at 3.3 v and the driver circuit operates at 3.3 or 5.0 v (selectable). the input data is digital data at 6 bits 3 dots, and 260,000 colors can be displayed in 64-value outputs g -corrected by the internal d/a converter and 11 external power supplies. because the clock frequency is 33 mhz min , the m pd16641 can be used in tft-lcd panels conforming to the vga standards. features ? precharge-less output buffer ? 64-value output by 11 external power supplies and internal d/a converter ? level of g -corrected power supply can be inverted ? output voltage range: 2.8 v p-pmax. (at supply voltage v dd2 of driver circuit = 3.0 v) 4.3 v p-pmax. (at supply voltage v dd2 of driver circuit = 4.5 v) ? cmos level input ? 6 bit (gray scale data) 3 dot input ? high-speed data transfer: f max. = 33 mhz min. (internal data transfer rate at supply voltage v dd1 of logic circuit = 3.0 v) ? 240 outputs ? supply voltage of driver circuit selectable (v sel = h: 3.3 v, v sel = l: 5.0 v) ? slim tcp ordering information part no. package m pd16641n- tcp (tab package) the tcp is custom-made. for details, consult nec
2 m m m m pd16641 1. block diagram 80-bit bidirectional shift register c 1 c 2 c 79 c 80 sthl v dd1 (3.3 v) v ss1 sthr r/l clk data register d 00 to 05 d 10 to 15 d 20 to 25 latch stb d/a converter v dd2 (3.3/5.0 v) v sel output buffer v ss2 s 1 s 2 s 3 s 240 v 0 to v 10
3 m m m m pd16641 2. pin configuration (standard tcp: m m m m pd16641n- ) common common v sel v ss2 v dd2 v 10 v 8 v 6 v 4 v 2 v 0 r/l d 20 d 21 d 22 d 23 d 24 d 25 stb sthl v dd1 clk v ss1 sthr d 10 d 11 d 12 d 13 d 14 d 15 d 00 d 01 d 02 d 03 d 04 d 05 v 1 v 3 v 5 v 7 v 9 v dd2 v ss2 common common common common nc nc nc common common common nc nc nc nc s 240 s 239 s 2 s 1 nc nc nc nc common common common nc nc nc common common common (copper foil surface) monitor pin monitor pin v sel pin is internally pulled up. therefore, the number of input pins can be reduced by opening or short-circuiting these pins to v ss2 by means of tcp wiring.
4 m m m m pd16641 3. pin description pin symbol pin name description s 1 to s 240 driver output output 64 gray scale analog voltages converted from digital signals. d 00 to d 05 d 10 to d 15 d 20 to d 25 display data input inputs 18-bit-wide display gray scale data (6 bits) 3 dots (rgb). d x0 : lsb, d x5 : msb r/l shift direction select input this pin inputs/outputs start pulses when two or more m pd16641s are connected in cascade. shift direction of shift register is as follows: r/l = h : sthr input, s 1 ? s 240 , sthl output r/l = l : sthl input, s 240 ? s 1 , sthr output sthr right shift start pulse i/o r/l = h : inputs start pulse. r/l = l : outputs start pulse. sthl left shift start pulse i/o r/l = h : outputs start pulse. r/l = l : inputs start pulse. v sel driver voltage selection selects driver voltage. this pin is internally pulled up to v dd2 . v sel = v dd2 or open: v dd2 = 3.3 v 0.3 v, v sel = l: v dd2 = 5.0 v 0.5 v clk shift clock input inputs shift clock to shift register. display data is loaded to data register at rising edge of this pin. start pulse output goes high at rising edge of 80th clock after start pulse has been input, and serves as start pulse to driver in next stage. 80th clock of driver in first stage serves as start pulse of driver in next stage. stb latch input contents of data register are latched at rising edge, transferred to d/a converter, and output as analog voltage corresponding to display data. contents of initial shift register are cleared after stb has been input. one pulse of this signal is input when m pd16641 is started, and then device operates normally. for stb input timing, refer to relations between stb, start pulse, and blanking period in switching characteristic waveform . v 0 to v 10 g -corrected power supply inputs g -corrected power from external source. v ss2 v 10 v 9 v 8 v 7 v 6 v 5 v 4 v 3 v 2 v 1 v 0 v dd2 v ss2 v 0 v 1 v 2 v 3 v 4 v 5 v 6 v 7 v 8 v 9 v 10 v dd2 maintain gray scale power supply during gray scale voltage output. v dd1 logic circuit power supply 3.3 v 0.3 v v dd2 driver circuit power supply v sel = v dd2 or open : v dd2 = 3.3 v 0.3 v v sel = l : v dd2 = 5.0 v 0.5 v v ss1 logic ground ground v ss2 driver ground ground caution be sure to turn on power in the order v dd1 , logic input, v dd2 , and gray scale power (v 0 to v 10 ), and turn off power in the reverse order, to prevent the m m m m pd16641 from being damaged by latchup. be sure to observe this power sequence even during a transition period.
5 m m m m pd16641 4. relation between input data and output voltage value the 11 major points on the g characteristic curve of the lcd panel are arbitrarily set by external power supplies v 0 through v 10 . if the display data is 00 h or 3f h , gray scale voltage v 0 or v 10 is output. if the display data is in the range 01 h to 3e h , the high-order 3 bits select an external powers pair v n+1 , v n . the low-order 3 bits evenly divide the range of v n+1 to v n into eight segments by means of d/a conversion (however, the ranges from v 9 to v 8 and from v 2 to v 1 are divided into seven segments) to output a 64 gray scale voltage. 3f 37 2f 27 1f 17 f 7 0 v 10 v ss2 v 9 v 8 v 7 v 6 v 5 v 4 v 3 v 2 v 1 v 0 v dd2 gray scale supply specified by 00 h 7 segments 8 segments 8 segments 8 segments 8 segments 8 segments 8 segments 7 segments gray scale supply specified by 3f h d x5 (msb) d x4 d x3 d x2 d x1 d x0 (lsb) high-order 3 bits: g -corrected power selected (v n+1 , v n ) low-order 3 bits: 3bit d/a (range v n to v n+1 is divided into 7 or 8 segments) d x5 0 0 0 0 1 1 1 1 d x4 0 0 1 1 0 0 1 1 d x3 0 1 0 1 0 1 0 1 v n+1 to v n v 1 to v 2 v 2 to v 3 v 3 to v 4 v 4 to v 5 v 5 to v 6 v 6 to v 7 v 7 to v 8 v 8 to v 9 v n 000 001 010 011 100 101 110 111 v n+1 1 2 3 4 5 6 7 8 input data (hex) d x2 to d x0
6 m m m m pd16641 relation between input data and output voltage input data d x5 d x4 d x3 d x2 d x1 d x0 output voltage 00 h 01 h 02 h 03 h 04 h 05 h 06 h 07 h 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 v 0 v 2 + (v 1 C v 2 ) 6/7 v 2 + (v 1 C v 2 ) 5/7 v 2 + (v 1 C v 2 ) 4/7 v 2 + (v 1 C v 2 ) 3/7 v 2 + (v 1 C v 2 ) 2/7 v 2 + (v 1 C v 2 ) 1/7 v 2 08 h 09 h 0a h 0b h 0c h 0d h 0e h 0f h 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 v 3 + (v 2 C v 3 ) 7/8 v 3 + (v 2 C v 3 ) 6/8 v 3 + (v 2 C v 3 ) 5/8 v 3 + (v 2 C v 3 ) 4/8 v 3 + (v 2 C v 3 ) 3/8 v 3 + (v 2 C v 3 ) 2/8 v 3 + (v 2 C v 3 ) 1/8 v 3 10 h 11 h 12 h 13 h 14 h 15 h 16 h 17 h 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 v 4 + (v 3 C v 4 ) 7/8 v 4 + (v 3 C v 4 ) 6/8 v 4 + (v 3 C v 4 ) 5/8 v 4 + (v 3 C v 4 ) 4/8 v 4 + (v 3 C v 4 ) 3/8 v 4 + (v 3 C v 4 ) 2/8 v 4 + (v 3 C v 4 ) 1/8 v 4 18 h 19 h 1a h 1b h 1c h 1d h 1e h 1f h 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 v 5 + (v 4 C v 5 ) 7/8 v 5 + (v 4 C v 5 ) 6/8 v 5 + (v 4 C v 5 ) 5/8 v 5 + (v 4 C v 5 ) 4/8 v 5 + (v 4 C v 5 ) 3/8 v 5 + (v 4 C v 5 ) 2/8 v 5 + (v 4 C v 5 ) 1/8 v 5 20 h 21 h 22 h 23 h 24 h 25 h 26 h 27 h 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 v 6 + (v 5 C v 6 ) 7/8 v 6 + (v 5 C v 6 ) 6/8 v 6 + (v 5 C v 6 ) 5/8 v 6 + (v 5 C v 6 ) 4/8 v 6 + (v 5 C v 6 ) 3/8 v 6 + (v 5 C v 6 ) 2/8 v 6 + (v 5 C v 6 ) 1/8 v 6 28 h 29 h 2a h 2b h 2c h 2d h 2e h 2f h 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 v 7 + (v 6 C v 7 ) 7/8 v 7 + (v 6 C v 7 ) 6/8 v 7 + (v 6 C v 7 ) 5/8 v 7 + (v 6 C v 7 ) 4/8 v 7 + (v 6 C v 7 ) 3/8 v 7 + (v 6 C v 7 ) 2/8 v 7 + (v 6 C v 7 ) 1/8 v 7 30 h 31 h 32 h 33 h 34 h 35 h 36 h 37 h 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 v 8 + (v 7 C v 8 ) 7/8 v 8 + (v 7 C v 8 ) 6/8 v 8 + (v 7 C v 8 ) 5/8 v 8 + (v 7 C v 8 ) 4/8 v 8 + (v 7 C v 8 ) 3/8 v 8 + (v 7 C v 8 ) 2/8 v 8 + (v 7 C v 8 ) 1/8 v 8 38 h 39 h 3a h 3b h 3c h 3d h 3e h 3f h 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 v 9 + (v 8 C v 9 ) 6/7 v 9 + (v 8 C v 9 ) 5/7 v 9 + (v 8 C v 9 ) 4/7 v 9 + (v 8 C v 9 ) 3/7 v 9 + (v 8 C v 9 ) 2/7 v 9 + (v 8 C v 9 ) 1/7 v 9 v 10
7 m m m m pd16641 g g g g -corrected power circuit the reference power supply of the d/a converter consists of a ladder circuit with a total of 64 resistors, and resistance s ri between g -corrected power pins differs depending on each pair of g -corrected power pins. one pair of g -corrected power pins consists of seven or eight series resistors, and resistance s ri in the figure below is indicated as the sum of the seven of eight resistors. the resistance ratio between the g -corrected power pins ( s ri ratio) is designed to be a value relatively close to the ratio of the g -corrected voltages v 1 through v 9 (gray scale voltages in 8 steps) used in an actual lcd panel. under ideal conditions where there is no difference between the two, therefore, there is no voltage difference between the voltage of the g -corrected power supplies and the gray scale voltages in 8 steps of the resistor ladder circuits of the m pd16641, and no current flows into the g -corrected power pins v 1 through v 9 . as a result, a voltage follower circuit is not necessary. C + v 0 i 0 C + v 1 i 1 C + v 2 i 2 C + v 3 i 3 C + v 4 i 4 C + v 5 i 5 C + v 6 i 6 C + v 7 i 7 C + v 8 i 8 C + v 9 i 9 C + v 10 i 10 r 0 = 1.81 k w r 1 = s r i = 3.57 k w r 9 = 13.5 k w i=1 7 r 2 = s r i = 3.12 k w i=1 8 r 3 = s r i = 3.08 k w i=1 8 r 4 = s r i = 2.90 k w i=1 8 r 5 = s r i = 2.32 k w i=1 8 r 6 = s r i = 3.35 k w i=1 8 r 7 = s r i = 3.23 k w i=1 8 r 8 = s r i = 4.75 k w i=1 7 g -corrected power pin g -corrected resistor pd16641 m sum of eight g -corrected resistors
8 m m m m pd16641 relation between input data and output data data format : 1 pixel data (6 bits) rgb (3 dots) input width : 18 bits r/l = h (right shift) output s 1 s 2 s 3 s 239 s 240 data d 00 to d 05 d 10 to d 15 d 20 to d 25 d 10 to d 15 d 20 to d 25 r/l = l (left shift) output s 1 s 2 s 3 s 239 s 240 data d 00 to d 05 d 10 to d 15 d 20 to d 25 d 10 to d 15 d 20 to d 25 5. operation of output buffer the output buffer consists of an operational amplifier circuit that does not perform precharge operation. therefore, driver output current i voh1/2 is the charging current to the lcd, and i vol1/2 is the discharging current . the chip has the driving capability to charge or discharge a liquid load with c l = 80 pf to 3 t in less than 10 m s. s n v dd2 v ss2 write (i vol /i voh ) write (i vol /i voh ) 1 horizontal period
9 m m m m pd16641 6. electric specification absolute maximum ratings (v ss1 = v ss2 = 0 v) parameter symbol rating unit supply voltage v dd1 C0.3 to +4.5 v supply voltage v dd2 C0.3 to +7.0 v input voltage v i C0.3 to v dd1, 2 + 0.3 v output voltage v o C0.3 to v dd1, 2 + 0.3 v permissible dissipation p d 150 mw operating temperature range t a C10 to +75 c storage temperature range t stg. C55 to +125 c recommended operating range (t a = C10 to +75c, v ss1 = v ss2 = 0 v) parameter symbol condition min. typ. max. unit logic supply voltage v dd1 3.0 3.3 3.6 v driver supply voltage v dd2 v sel = h 3.0 3.3 3.6 v driver supply voltage v dd2 v sel = l 4.5 5.0 5.5 v g -corrected power v 0 to v 10 v ss2 + 0.1 v dd2 C 0.1 v maximum clock frequency f max. 33 mhz output load capacitance c l 150 pf
10 m m m m pd16641 electrical characteristics (t a = C10 to +75c, v dd1 = 3.0 to 3.6 v, v dd2 = 3.0 to 3.6 v or 4.5 to 5.5 v, v ss1 = v ss2 = 0 v) parameter symbol condition min. typ. max. unit high-level input voltage v ih 0.7v dd1 v dd1 v low-level input voltage v il r/l, clk, stb, sthr (l), d 00-05 , d 10-15 , d 20-25 00.3v dd1 v input leakage current i l d 00-05 , d 10-15 , d 20-25 r/l, clk, stb, sthr (l) 1.0 m a pull-up resistor r pu v sel , v dd2 = 5.0 v, v sel , = 0 v 40 100 250 k w high-level output voltage v oh sthr (l), i o = C1.0 ma v dd1 C 0.5 v low-level output voltage v ol sthr (l), i o = +1.0 ma 0.5 v v 10 C200 C150 m a v 9 to v 1 10 m a static current consumption of g -corrected power (v dd2 = 3.3 v) i vn1 v dd1 = 3.3 v, v dd2 = 3.3 v v 0 = 3.20 v, v 6 = 1.95 v v 1 = 3.07 v, v 7 = 1.70 v v 2 = 2.80 v, v 8 = 1.46 v v 3 = 2.57 v, v 9 = 1.11 v v 4 = 2.34 v, v 10 = 0.10 v v 5 = 2.12 v, note v 0 150 200 m a v 10 C300 C250 m a v 9 to v 1 10 m a static current consumption of g -corrected power (v dd2 = 5.0 v) i vn2 v dd1 = 3.3 v, v dd2 = 5.0 v v 0 = 4.90 v, v 6 = 2.96 v v 1 = 4.69 v, v 7 = 2.58 v v 2 = 4.28 v, v 8 = 2.20 v v 3 = 3.92 v, v 9 = 1.66 v v 4 = 3.56 v, v 10 = 0.1 v v 5 = 3.23 v, note v 0 250 300 m a (v x is output voltage of analog output pin s 1 to s 240 . v out is the voltage applied to analog output pin s 1 to s 240 .) note apply ideal voltage to v 1 to v 9 that is calculated from internal resistor.
11 m m m m pd16641 electrical characteristics (t a = C10 to +75c, v dd1 = 3.0 to 3.6 v, v dd2 = 3.0 to 3.6 v or 4.5 to 5.5 v, v ss1 = v ss2 = 0 v) parameter symbol condition min. typ. max. unit i voh1 stb = 3.3 v v out = 2.2 v, v x = 3.2 v v dd1 = v dd2 = 3.3 v C0.3 C0.075 ma driver output current (v dd2 = 3.3 v) i vol1 stb = 3.3 v v out = 1.1 v, v x = 0.1 v v dd1 = v dd2 = 3.3 v 0.075 0.25 ma i voh2 stb = 5.0 v v out = 3.9 v, v x = 4.9 v v dd1 = 3.3 v, v dd2 = 5.0 v C0.3 C0.1 ma driver output current (v dd2 = 5.0 v) i vol2 stb = 5.0 v v out = 1.1 v, v x = 0.1 v v dd1 = 3.3 v, v dd2 = 5.0 v 0.1 0.25 ma v dd1 = 3.3 v, v dd2 = 3.3 v v out = 1.65 20 25 mv output voltage deviation d v o v dd1 = 3.3 v, v dd2 = 5.0 v v out = 2.50 v 20 25 mv output voltage range v o input data: 00 h to 3f h v ss2 + 0.1 v dd2 C 0.1 v dynamic logic current consumption i dd1 no load note 2.0 ma dynamic driver current consumption i dd21 no load, v dd2 = 3.3 v 0.3 v note 5.0 ma dynamic driver current consumption i dd22 no load, v dd2 = 5.0 v 0.5 v note 6.5 ma note the stb cycle is specified at 31 m s and f clk = 16 mhz. input data: 1010 (checkerboard pattern) refers to current consumption per driver when cascades are connected under the assumption of vga single-sided mounting (8 units).
12 m m m m pd16641 switching characteristics (t a = C10 to +75c, v dd1 = 3.0 to 3.6 v, v dd2 = 3.0 to 3.6 v or 4.5 to 5.5 v, v ss1 = v ss2 = 0 v, t r = t f = 3.0 ns) parameter symbol condition min. typ. max. unit start pulse delay time t plh1 c l = 15 pf 2.0 17 ns start pulse delay time t phl1 c l = 15 pf 2.0 17 ns driver output delay time 1 t plh21 6.0 12 m s driver output delay time 2 t plh31 v o : 0.1 v ? 3.2 v 8.0 14 m s driver output delay time 1 t phl21 6.0 10 m s driver output delay time 2 t phl31 v dd2 = 3.3 v 2 k w + 75 pf 2 v o : 3.2 v ? 0.1 v 8.0 12 m s driver output delay time 1 t plh22 6.0 10 m s driver output delay time 2 t plh32 v o : 0.1 v ? 4.9 v 8.0 12 m s driver output delay time 1 t phl22 6.0 8.0 m s driver output delay time 2 t phl32 v dd2 = 5.0 v 2 k w + 75 pf 2 v o : 4.9 v ? 0.1 v 8.0 10 m s input capacitance c i1 v 0 to v 10 , t a = 25c 100 pf input capacitance c i2 sthr (l), t a = 25c 10 15 pf input capacitance c i3 sthr (l), other than v 0 to v 10 t a = 25c 7.0 10 pf timing requirements (t a = C10 to +75c, v dd1 = 3.0 to 3.6 v, v dd2 = 3.0 to 3.6 v or 4.5 to 5.5 v, v ss1 = v ss2 = 0 v, t r = t f = 3.0 ns) parameter symbol condition min. typ. max. unit clock pulse width pw clk 22 ns clock low period pw clk(l) 4.0 ns clock high period pw clk(h) 4.0 ns data setup time t setup1 2.0 ns data hold time t hold1 2.0 ns start pulse setup time t setup2 2.0 ns start pulse hold time t hold2 2.0 ns start pulse low period t spl 2clk start pulse rise time t spr 80 clk stb setup time t setup3 1clk data invalid period t inv 1clk final data timing t ldt 1clk clk-stb time t clk-stb clk - ? stb - or 7.0 ns stb-clk time t stb-clk stb - or ? clk - 7.0 ns
13 m m m m pd16641 7. switching characteristic waveform (r/l = h) unless otherwise specified, the input level is v ih = 0.7 v dd1 , v il = 0.3 v dd1 . clk v dd1 v ss1 d xx v dd1 v ss1 sthr (sthl) v dd1 v ss1 sthl (sthr) v dd1 v ss1 stb v dd1 v ss1 t hold1 t setup1 s n s n pw clk pw clk (h) pw clk (l) t f t r 90 % 10 % 90 % 10 % t hold2 t spl t setup2 t hold2 t setup3 t spr1/2 t plh1 t phl1 v ih t phl31/32 t phl21/22 t phl31/32 t phl21/22 targeted output voltage ?0.1v dd2 targeted output voltage ?0.1v dd2 targeted output voltage (6-bit accuracy) the figures in parenthesis indicate r/l = l
14 m m m m pd16641 switching characteristic waveform clk v dd1 v ss1 sthr (sthl) v dd1 v ss1 d xx v dd1 v ss1 clk v dd1 v ss1 stb v dd1 v ss1 d xx v dd1 v ss1 clk v dd1 v ss1 stb v dd1 v ss1 1234 638 639 640 641 642 1234 638 639 640 t inv t setup2 t hold2 t setup1 t hold1 t ldt (1 clk max. ) t setup1 t hold1 t clk-stb t stb-clk t clk-stb t stb-clk
15 m m m m pd16641 8. relation between stb/sthr, sthl and blanking period clk d xx (640th line) d xx (1st line) stb 1st sthr (in) 641 642 643 644 1 2 640 12 v ih v il v ih v il t blk (4 clk min. ) t clk-stb (7 ns min. ) t stb-clk (7 ns min. ) t ldt (1 clk min. ) t setup2 (4 ns min. ) t hold2 (0 ns min. ) t setup3 (2 clk min. )
16 m m m m pd16641 9. data input timing in cascade connection clk 78 79 80 81 82 83 84 1st d xx (in) 1st sthl (out) 2nd sthr (in) 2nd d xx (in) 78 79 80 77 123 clk stb output hi-z output
17 m m m m pd16641 10. recommended mounting conditions mounting this product under the following conditions is recommended. for the mounting methods and conditions other than those recommended, consult nec. mounting conditions mounting method conditions soldering heating tool: 300 to 350c, heating time: 2 to 3 seconds, pressure: 100 g (per product) thermocompression bonding acf (sheet adhesive) preliminary adhesion: 70 to 100c, pressure: 3 to 8 kg/cm 2 , time: 3 to 5 seconds real adhesion: 165 to 180c, pressure: 25 to 45 kg/cm 2 , time 30 to 40 seconds (when sumizac1003 of sumitomo bakelite is used) note for the mounting conditions for acf, consult the acf manufacturer. do not use two or more mounting methods in combination. reference nec semiconductor device reliability/quality control system (c10983e) quality grades to necs semiconductor devices (c11531e)
18 m m m m pd16641 [memo]
19 m m m m pd16641 [memo]
m m m m pd16641 no part of this document may be copied or reproduced in any form or by any means without the prior written consent of nec corporation. nec corporation assumes no responsibility for any errors which may appear in this document. nec corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device. no license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of nec corporation or others. while nec corporation has been making continuous effort to enhance the reliability of its semiconductor devices, the possibility of defects cannot be eliminated entirely. to minimize risks of damage or injury to persons or property arising from a defect in an nec semiconductor device, customers must incorporate sufficient safety measures in its design, such as redundancy, fire-containment, and anti-failure features. nec devices are classified into the following three quality grades: "standard", "special", and "specific". the specific quality grade applies only to devices developed based on a customer designated "quality assurance program" for a specific application. the recommended applications of a device depend on its quality grade, as indicated below. customers must check the quality grade of each device before using it in a particular application. standard: computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots special: transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) specific: aircrafts, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems or medical equipment for life support, etc. the quality grade of nec devices is "standard" unless otherwise specified in nec's data sheets or data books. if customers intend to use nec devices for applications other than those specified for standard quality grade, they should contact an nec sales representative in advance. anti-radioactive design is not implemented in this product. m4 96. 5

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